<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Analog &amp; Mixed-Signal on Américo Dias</title><link>https://americo.dias.pt/categories/analog--mixed-signal/</link><description>Recent content in Analog &amp; Mixed-Signal on Américo Dias</description><generator>Hugo</generator><language>en</language><lastBuildDate>Thu, 15 Oct 2026 21:29:12 +0000</lastBuildDate><atom:link href="https://americo.dias.pt/categories/analog--mixed-signal/index.xml" rel="self" type="application/rss+xml"/><item><title>The Future of Analog IC Design with Agentic AI</title><link>https://americo.dias.pt/posts/analog-design-ai-agents/</link><pubDate>Tue, 13 Oct 2026 08:05:13 +0100</pubDate><guid>https://americo.dias.pt/posts/analog-design-ai-agents/</guid><description>&lt;p&gt;The interesting part of handing two analog blocks to an AI agent was not that it sized every transistor. It was that it could hold the specification, the implementation, the verification state and the project record at the same time, change one of them, and bring the rest back into agreement without being told to.&lt;/p&gt;
&lt;p&gt;That is a different thing from automation, and it points somewhere larger than a single block. It moves the engineer away from carrying every assumption through every representation by hand, and towards defining intent, encoding constraints, judging trade-offs and controlling a continuously verified loop.&lt;/p&gt;</description></item><item><title>Radio-Frequency Transmitter for Subcutaneous Biomedical Implants</title><link>https://americo.dias.pt/posts/thesis/</link><pubDate>Sun, 24 Jun 2018 08:30:00 +0100</pubDate><guid>https://americo.dias.pt/posts/thesis/</guid><description>&lt;!--
*[A/D]: Analog-to-digital converter
*[AWGN]: Additive white Gaussian noise
*[BPSK]: Binary phase shift keying
*[CMOS]: Complementary metal–oxide–semiconductor
*[DRC]: Design rule check
*[DSO]: Digital sampling oscilloscope
*[DSSS]: Direct-sequence spread spectrum
*[EIRP]: Equivalent isotropically radiated power
*[FCC]: Federal Communications Commission
*[FF]: Fast NMOS and fast PMOS
*[FS]: Fast NMOS and slow PMOS
*[FSK]: Frequency-shift keying
*[GPS]: Global positioning system
*[IFN]: Integrate-and-fire neuron
*[IR-UWB]: Impulse-radio ultra-wideband
*[LNA]: Low-noise amplifier
*[LTCC]: Low-temperature co-fired ceramic
*[LVS]: Layout-versus-schematic
*[MB-OFDM]: Multi band orthogonal frequency-division multiplexing
*[MB-UWB]: Multi-band ultra-wideband
*[MOSFET]: Metal–oxide–semiconductor field-effect transistor
*[MSK]: Minimum-shift keying
*[NMOS]: N-channel metal–oxide–semiconductor transistor
*[OFDM]: Orthogonal frequency-division multiplexing
*[OOK]: On-off keying
*[PA]: Power amplifier
*[PAE]: Power added efficiency
*[PAM]: Pulse amplitude modulation
*[PEX]: Parasitic extraction
*[PHY]: Physical layer
*[PMOS]: P-channel metal–oxide–semiconductor transistor
*[PN]: Pseudo noise
*[PPM]: Pulse position modulation
*[PRF]: Pulse repetition frequency
*[PSD]: Power spectral density
*[RF]: Radio-frequency
*[SF]: Slow NMOS and fast PMOS
*[SNR]: Signal-to-noise ratio
*[SS]: Slow NMOS and slow NMOS
*[TSMC]: Taiwan Semiconductor Manufacturing Company
*[TT]: Typical NMOS and typical PMOS
*[UMC]: United Microelectronics Corporation
*[UWB]: Ultra-wideband
*[VCO]: Voltage controlled oscillator
*[IoT]: Internet of Things
--&gt;
&lt;h2 id="about"&gt;About this edition&lt;/h2&gt;
&lt;p&gt;Publishing a web-edition of my master&amp;rsquo;s thesis report was a project that I kept
delaying over the last years. Finally I had time to work on it. This report was
delivered almost 7 years ago - at the time of writing - in June 2010.&lt;/p&gt;</description></item><item><title>Phase Locked Loop Simulator in SystemC-AMS</title><link>https://americo.dias.pt/posts/pll/</link><pubDate>Fri, 02 Mar 2018 08:30:00 +0100</pubDate><guid>https://americo.dias.pt/posts/pll/</guid><description>&lt;h2 id="1-introduction"&gt;1. Introduction&lt;/h2&gt;
&lt;p&gt;When I started to learn SystemC-AMS one of the first circuits I decided to
implement was a Phase Locked Loop. The reason for this is because I have had an
experience &lt;a href="https://web.archive.org/web/20160523165857/http://usgroup.eu/activities/projects/wireless_front-end/" target="_blank" rel="noopener noreffer "&gt;simulating a 2.4GHz
PLL&lt;/a&gt;
while I was &lt;a href="https://web.archive.org/web/20150715000110/http://usgroup.eu:80/blog/author/adias/" target="_blank" rel="noopener noreffer "&gt;member of the Microelectronics Student&amp;rsquo;s
Group&lt;/a&gt;,
and I realized how difficult is to simulate such circuit, specially when the
output and the reference frequency are several orders of magnitude apart. The
simulator has to use a small time-step to accommodate the higher frequency but
at the same time, the PLL will take a relatively long time to lock and reach the
steady state.&lt;/p&gt;</description></item></channel></rss>